As semiconductor elements have been miniaturized, distances between sources and drains of MOS transistors are reduced and leakage currents between the sources and the drains are increased. The leakage currents are increased in an exponential manner along with increase of operation temperatures of the MOS transistors. The leakage currents are further increased when a threshold value is lowered owing to fabrication variations of the MOS transistors. Therefore, in semiconductor integrated circuits including the MOS transistors, power consumptions are increased owing to increase of the leakage currents.
Accordingly, in micro processors, for example, a method, which is referred to as a Dynamic Voltage and Frequency Scaling (DVFS) method, for reducing a power consumption using a circuit function of changing a power-supply voltage of an internal circuit or a frequency of an operation clock in accordance with a processing load has been employed.
Furthermore, in mobile devices, a method, which is referred to as a Power Gating) (PG method, for reducing a power consumption by stopping power supplied to an internal circuit while the internal circuit is in a standby state has been employed.
According to the DVFS method, an operation current and a leakage current per unit time may be reduced by controlling an operation frequency or an operation voltage of a task having long Worst Case Execution Time (WCET) so that operation periods of circuits are matched with one another. For example, Japanese Laid-open Patent Application Publication No. 2001-345693 discloses a semiconductor integrated circuit device capable of controlling a clock control circuit and a power-supply voltage control circuit in accordance with requisite performance so as to realize a low power consumption.
On the other hand, according to the PG method, although the operation current and the leakage current while the circuits operate are not reduced, a leakage current while the circuits do not operate in the WCET is reduced.
As described above, in terms of the reduction of the power consumption, one of the DVFS method and the PG method has been used depending on an operation of a circuit included in a semiconductor integrated circuit device and a state of a WCET associated with the circuit operation. However, superiority of the DVFS method or the PG method in a certain semiconductor integrated circuit device may depend on an operation temperature condition and a fabrication condition of the semiconductor integrated circuit device.